1. Field of the Invention
The present invention relates to a method of manufacturing a wafer used to manufacture semiconductor devices, and more particularly, to a method of manufacturing a semiconductor wafer capable of manufacturing high-quality devices by shortening time taken to manufacture the wafer and improving the concentration of an impurity.
2. Background of the Related Art
Recently, as semiconductor devices become rapidly ultra-higher integrated and the hole of the wafers become rapidly larger, a technology to improve the quality of the wafer for manufacturing the semiconductor devices becomes an important problem. If there exists even the minimum of an impurity, lattice defect, and the like in the wafer of a device-driven region, it is required that generation of these impurity, lattice defect, etc. be prohibited or removed in a process of manufacturing the wafer since they greatly affects electrical characteristics of the device.
In a prior art, the impurity, the lattice defect, and the like existing in the wafer were removed using internal gettering through three step annealing processes, as shown in FIG. 1.
There are a large amount of supersaturated oxygen in a single crystal silicon wafer grown by Czochralski method. Therefore, in order to diffuse oxygen existing on the surface of the wafer, the wafer is loaded into the furnace and is then annealed at a temperature of 1000˜1200° C. for 1˜2 hours. Next, the wafer is annealing at a temperature of 650˜850° C. for 3˜10 hours to form a nucleation site at a region deep into the wafer. Thereafter, if the wafer is annealing at a temperature of 900˜1000° C. for 1˜4 hours, oxygen precipitation material, an metallic impurity, or the like are trapped in the nucleation site, so that a defect layer is formed at a region deep into the wafer.
As described above, in the prior art, the concentration of oxygen in the device-driven region is controlled by forming a defect layer in which the oxygen precipitation material, the metallic impurity, etc. are gettered at a desired region of the wafer, i.e. outside the device-driven region through three-step annealing processes of high-temperature, low temperature and medium temperature. At this time, the size and location of the defect layer may be artificially adjusted depending on the annealing temperature and time. If the conventional method is used, however, there is a disadvantage that the productivity is low since many annealing steps are required, lots of time is wasted and lots of time is also taken to manufacture the wafer.